I. Field of the Disclosure
The technology of the disclosure relates generally to semiconductor packaging of semiconductor dies and passive components, and more specifically to minimizing undesirable inductance interference between the passive components and a ground plane of circuit board to which the semiconductor package is mounted.
II. Background
Semiconductor packages typically involve one or more semiconductor dies integrated on a substrate, such as a glass substrate. The substrate is then attached to a package base, such as a printed circuit board (PCB). Passive components such as capacitors and inductors are usually formed on one side, such as a lower side, of the substrate. The substrate may be attached to the PCB, face down, such that the lower side having the passive components is closest to the PCB. Ball grid arrays (BGAs) including solder balls may be utilized for forming the connections and attachment between the substrate and the PCB. Electrical connections between the PCB and the substrate may be formed with wire bonds and pads.
For example, with reference to FIG. 1, a side view of a conventional semiconductor package 100 is illustrated. The conventional semiconductor package 100 includes a glass substrate 102 with an inductor 104 attached on a lower surface 106 of the glass substrate 102. The combination of the glass substrate 102 with the inductor 104 is referred to as a two-dimensional (2D) passive-on-glass (POG) structure. The 2D POG structure is attached to a PCB 108 using solder balls 110 that form one or more BGAs 112. The PCB 108 includes a ground plane 114. For example, the ground plane 114 may be a large area of copper foil which is connected to a ground terminal (not shown) of the PCB 108, and serves as a ground or return path for current from the various components integrated on the PCB 108.
With continuing reference to FIG. 1, the inductor 104 is vertically separated from the ground plane 114 by a separation distance D0. An increased separation distance D0 minimizes undesirable inductance interference and accompanying quality factor (Q-factor) degradation between the inductor 104 and the ground plane 114. A conventional approach for fabricating the conventional semiconductor package 100 relies on the BGAs 112 to control the separation distance D0 between the inductor 104 and the ground plane 114 in the PCB 108. However, it may be difficult to achieve a desired and consistent height H0 of the solder balls 110 that form the BGAs 112. In addition, the solder balls 110 may also tend to be highly susceptible to reflow degradation, which can cause the separation distance D0 to vary (e.g., decrease), as a result. Furthermore, over the course of operation, the reflow degeneration of the solder balls 110 may lead to collapse of the 2D POG structure in the conventional semiconductor package 100 due to high heat and stress that is common in semiconductor packages like the conventional semiconductor package 100. In this regard, there is a need for efficient and reliable integration of the 2D POG structure to avoid the aforementioned problems.